Browsing by Author "Pei, Zhenlin"
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Publication Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application
Journal article2022, IEEE TRANSACTIONS ON NANOTECHNOLOGY, 21, p.367-373Publication CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
Journal article2023, IEEE TRANSACTIONS ON ELECTRON DEVICES, (70) 10, p.5099-5106Publication Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes
Journal article2024, IEEE EMBEDDED SYSTEMS LETTERS, (16) 4, p.321-324Publication Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access
Proceedings paper2023, 24th International Symposium on Quality Electronic Design (ISQED), APR 05-07, 2023, p.209-209Publication Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect
Journal article2024, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, (71) 12, p.6495-6506Publication Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes
Journal article2023-01-01, IEEE TRANSACTIONS ON ELECTRON DEVICES, (70) 1, p.230-238Publication Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
Proceedings paper2023, 33rd Great Lakes Symposium on VLSI (GLSVLSI), JUN 05-07, 2023, p.159-162Publication Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus
Journal article2024, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, (71) 10, p.4597-4610