Browsing by Author "Perello, Carles"
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Publication A high performance 0.18µm elevated source/drain technology with improved manufacturability
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference, 13/09/1999, p.636-639Publication A high performance of 0.18μm CMOS technology designed for manufacturability
Proceedings paper1997, ESSDERC '97: Proceedings of the 27th European Solid-State Device Research Conference, 22/09/1997, p.404-407Publication A new dummy-free shallow trench isolation concept for mixed-signal applications
Publication A new dummy-free shallow trench isolation concept for mixed-signal applications
Publication Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity
Journal article2000, IEEE Trans. Electron Devices, (47) 7, p.1484-1491Publication L-shape spacer architecture for low cost, high performance CMOS
Publication Optimisation of critical parameters in a low cost, high performance deep submicron CMOS technology
Publication Test structures for MCM-D technology characterization