Browsing by Author "Raghavan, Praveen"
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Publication 2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms
Proceedings paper2014, IEEE International Interconnect Technology Conference - IITC, 20/05/2014, p.381-384Publication 2PARMA: Parallel paradigms and run-time management techniques for many-core architectures
Publication 2PARMA: Parallel paradigms and run-time management techniques for many-core architectures
Publication 5nm: has the time for a device change come?
Proceedings paper2016, 17th International Symposium on Quality Electronic Design - ISQED, 15/03/2016, p.275-277Publication A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE
Proceedings paper2010, Symposium on VLSI Circuits, 16/06/2010, p.213-214Publication A 200Mbps+ 2.14nJ/b digital baseband multi processor system-on-chip for SDRs
Proceedings paper2009, Symposium on VLSI Circuits, 16/06/2009, p.292-293Publication A customized cross-bar for data-shuffling in domain-specific SIMD processors
Proceedings paper2007-03, Architecture of Computing Systems - ARCS, 12/03/2007, p.57-68Publication A flexible platform architecture for Gbps wireless communication
Proceedings paper2012, International Symposium on System-on-Chip - SoC, 11/10/2012Publication A multi-threaded, coarse-grained array processor for wireless baseband
Oral presentation2011, 49th Design Automation Conference - DACPublication A multi-threaded, coarse-grained array processor for wireless baseband
Proceedings paper2011, 9th IEEE Symposium on Application Specific Processors - SASP, 5/06/2011, p.102-107Publication A processor based multi-standard low-power LDPC engine for multi-GPS wireless communication
Proceedings paper2013, IEEE 1st Global Conference on Signal and Information Processing - GlobalSIP, 3/12/2013Publication A programmable low energy massive-parallel architecture for wireless communication systems
Oral presentation2011, DATE, Workshop on ArchitecturesPublication A smaller, faster and more energy-efficient complementary STT-MRAM cell uses three transistors and a ground grid: more is actually less
Journal article2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (25) 4, p.1204-1214Publication A soft-output Near-ML MIMO baseband receiver for 75Mbps+ SDR
Publication A unified instruction set programmable architecture for multi-standard advanced forward error correction
Publication Algorithm-architecture co-optimization of area-efficient SDR baseband for highly diversified digital TV standards
Proceedings paper2012, IEEE 75th Vehicular Technology Conference - VTCSpring, 6/05/2012, p.1-5Publication An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard
Proceedings paper2013, IEEE Workshop on Signal Processing Systems - SiPS, 16/10/2013, p.112-117Publication An efficient memory organization for high-ILP inner modem baseband SDR processors
Journal article2010, Journal of Signal Processing Systems, (61) 2, p.157-179Publication An energy aware design space exploration for VLIW AGU model with fine grained power gating
Proceedings paper2011, 14th Euromicro Conference on Digital System Design - DSD, 31/08/2011, p.693-700Publication An highly-efficient processor template for wireless communication systems
Oral presentation2012, Design. Automation. and Test in Europe Conference - DATE: PhD Forum