Browsing by Author "Riedel, Samuel"
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Publication 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs
Proceedings paper2024, IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-22, 2024Publication Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC
Journal article2025, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (33) 2, p.346-357Publication Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs
Journal article2024, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, (43) 7, p.1957-1970Publication MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration