Browsing by Author "Sathanur, Ashoka"

Activity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs

Automatic synthesis of near-threshold circuits with fine-grained performance tunability

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Leakage control in SoCs

Leakage current mechanisms and estimation in memories and logic

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications