Browsing by Author "Venezia, Vincent"
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Publication CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges
Proceedings paper2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.15-22Publication Enhanced low temperature electrical activation of B in Si
Publication Gate dielectrics for high performance and low power CMOS SoC applications
Publication The RF potential of high-performance 100nm CMOS technology