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CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges
Publication:
CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges
Date
2003
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Dachs, Charles
;
Surdeanu, Radu
;
Pawlak, Bartek
;
Doornbos, Gerben
;
Duffy, R.
;
Heringa, Anco
;
Ponomarev, Youri
;
Venezia, Vincent
;
Van Dal, Mark
;
Stolk, P.
;
Lindsay, Richard
;
Henson, Kirklen
;
Dieu, B.
;
Geenen, Luc
;
Hoflijk, Ilse
;
Richard, Olivier
;
Clarysse, Trudo
;
Brijs, Bert
;
Vandervorst, Wilfried
;
Pagès, Xavier
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2015
since deposited on 2021-10-15
Acq. date: 2025-10-22
Citations
Metrics
Views
2015
since deposited on 2021-10-15
Acq. date: 2025-10-22
Citations