Browsing by Author "Vengattaramane, Kameswaran"
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Publication A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS
Proceedings paper2009, IEEE Radio Frequency Integrated Circuits Symposium - RFIC, 7/06/2009, p.321-324Publication A 2mm2 0.1-5GHz SDR receiver in 45nm digital CMOS
Proceedings paper2009, IEEE International Solid-State Circuits Conference - ISSCC, 8/02/2009, p.408-409Publication A 2mm2 0.1-5GHz software defined radio receiver in 45nm digital CMOS
Journal article2009, IEEE Journal of Solid-State Circuits, (44) 12, p.3486-3498Publication A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS
Proceedings paper2010, IEEE Radio Frequency Integrated Circuits Conference - RFIC, 23/05/2010, p.417-420Publication A 86MHz-12GHz Digital-Intensive PLL for software-defined radios, using a 6fJ/step TDC in 40nm digital CMOS
Journal article2010, IEEE Journal of Solid-State Circuits, (45) 10, p.2116-2129Publication A 86MHz-12GHz digital-intensive, phase-modulated fractional-N PLL, using a 15pJ/shot 5ps TDC in 40nm digital CMOS
Proceedings paper2010, IEEE International Solid-State Circuits Conference - ISSCC, 7/02/2010, p.480-481Publication A gated ring oscillator based parallel-TDC with digital resolution enhancement
Proceedings paper2009, 5th IEEE Asian Solid-State Circuits Conference - A-SSCC, 16/11/2009Publication A standard cell based all-digital time-to-digital converter with reconfigurable resolution and on-line background calibration
Proceedings paper2011-09, 37th European Solid-State Circuits Conference - ESSCIRC, 12/09/2011, p.275Publication Analysis of fractional spur reduction using SD noise cancellation in digital PLL
Proceedings paper2009, IEEE International Conference on Circuits and Systems - ISCAS, 24/05/2009, p.2397-2400Publication Spatially oversampled TDC with resolution enhancement
Journal article2012, Analog Integrated Circuits and Signal Processing, (70) 3, p.311-322