Browsing by Author "Verbruggen, Bob"

A 0.9V 0.4-6GHz harmonic recombination SDR receiver in 28nm CMOS with HR3/HR5 and IIP2 calibration

A 1.7mW 11b 250MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS

A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS

A 150kHz-80MHz BW discrete-time analog baseband for aoftware-defined-radio receivers using a 5th-order IIR LPF, active FIR and a 10 bit 300 MS/s ADC in 28nm CMOS

A 150MS/s 133uW 7b ADC in 90nm digital CMOS using a comparator-based asynchronous binary search sub-ADC

A 150MS/s 133μW 7bit ADC in 90nm digital CMOS

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibrationn in 28nm digital CMOS

A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS

A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS

A 2.4 GHz Low Power 6th Order RF Bandpass \Delta \Sigma converter in CMOS

A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass \Sigma \Delta ADC in 90nm CMOS

A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm Digital CMOS

A 2.6mW 6b 2.2GS/s 4-times interleaved fully-dynamic pipelined ADC in 40nm digital CMOS

A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS

A 40nm CMOS 0.4-6 GHz receiver resilient to out-of-band blockers

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation

A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS

A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range