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A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS
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A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS
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Date
2014
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Spagnolo, Annachiara
;
Verbruggen, Bob
;
D'amico, Stefano
;
Wambacq, Piet
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Views
2002
since deposited on 2021-10-22
1
last month
1
last week
Acq. date: 2025-12-10
Citations