Browsing by Author "Waite, Andrew"
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Publication A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Proceedings paper2015-06, IEEE Symposium on VLSI Technology, 15/06/2015, p.30-31Publication Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature phosphorus extension ion implantation
Journal article2019, Solid-State Electronics, 152, p.58-64