Browsing by Author "van Meer, Hans"

70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme

A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with halos or pockets

A 2D analytical threshold voltage model for fully depleted short channel SOI MOSFET, inculding HALO

Analysis of halo implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature

Bias-dependent low-frequency noise model for low phase noise InP HEMT based MMIC oscillator design

Comparison between 0.13 μm partially depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K

Comprehensive study of Ga Activation in Si, SiGe and Ge and 5 x 10-10 $Xcm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation

Design, fabrication and charactisation of a 20 GHz low phase noise oscillator

Effect of Schottky barrier alteration on the low-frequency noise of InP-based HEMT's

Emerging device solutions for the post-classical CMOS era

Empirical modeling of the low-frequency noise behaviour of InP-baseds HEMTs

Fully-depleted SOI CMOS for the nanometer era

High performance raised gate/source/drain transistors for sub-0.15 μm CMOS technologies

IM3 suppression using a technology independent method based on vectorial large-signal measurements

Improved HEMT model for low phase-noise InP-based MMIC oscillator

Improved LOCOS isolation for ultra thin 0.18 μm fully-depleted SOI CMOS

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Influence of HALO implantation on analog performance and comparison between bulk, partially-depleted and fully-depleted MOSFET's

InP-based heterostructures for low-noise and power applications

Investigation of charge control related performances in double-gate SOI MOSFETs