Browsing by author "Marien, Philippe"

Now showing items 1-7 of 7

    • Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond 

      Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

    • Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh Bao, Trong; Eneman, Geert; Hellings, Geert; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • Improving uniformity of 3-level High Aspect Ratio Supervias 

      Montero Alvarez, Daniel; Marien, Philippe; Hermans, Yannick; Vega Gonzalez, Victor; Feurprier, Y.; Oikawa, N.; Buccheri, Nunzio; Wu, Chen; Martinez Alanis, Gerardo Tadeo; Batuk, Dmitry; Puliyalil, Harinarayanan; Decoster, Stefan; Kumar, K.; Lazzarino, Frederic; Murdoch, Gayle; Park, Seongho; Tokei, Zsolt (2023)

    • Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster 

      Marien, Philippe; Vega Gonzalez, Victor; Choudhury, Subhobroto; Radisic, Dunja; Decoster, Stefan; Kundu, Shreya; Hermans, Yannick; Kenens, Bart; De Coster, Hanne; Altamirano Sanchez, Efrain; Peter, Antony; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Batuk, Dmitry; Ryckaert, Julien; Murdoch, Gayle; Park, Seongho; Tokei, Zsolt (2023)

    • Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails 

      Veloso, Anabela; Jourdain, Anne; Radisic, Dunja; Chen, Rongmei; Arutchelvan, Goutham; O'Sullivan, Barry; Arimura, Hiroaki; Stucchi, Michele; De Keersgieter, An; Hosseini, Maryam; Hopf, Toby; D'have, Koen; Wang, Shouhua; Dupuy, Emmanuel; Mannaert, Geert; Vandersmissen, Kevin; Iacovo, Serena; Marien, Philippe; Choudhury, Subhobroto; Schleicher, Filip; Sebaai, Farid; Oniki, Yusuke; Zhou, X.; Gupta, Anshul; Schram, Tom; Briggs, Basoene; Lorant, Christophe; Rosseel, Erik; Hikavyy, Andriy; Loo, Roger; Geypen, Jef; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Soulie, Jean-Philippe; Devriendt, Katia; Chan, BT; Demuynck, Steven; Hiblot, Gaspard; Van der Plas, Geert; Ryckaert, Julien; Beyer, Gerald; Dentoni Litta, Eugenio; Beyne, Eric; Horiguchi, Naoto (2022)

    • Two-level Semi-damascene interconnect with fully self-aligned Vias at MP18 

      Marti, Giulio; Pokhrel, Ankit; Murdoch, Gayle; Delie, Gilles; Gupta, Anshul; Marien, Philippe; Lesniewska, Alicja; Decoster, Stefan; Kundu, Souvik; Le, Quoc Toan; Oniki, Yusuke; Kenens, Bart; Hermans, Yannick; Park, Seongho; Tokei, Zsolt (2023)