Browsing by author "Serbulova, Kateryna"
Now showing items 1-8 of 8
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CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
Horiguchi, Naoto; Mertens, Hans; Ritzenthaler, Romain; Subramanian, Sujith; Weckx, Pieter; Schuddinck, Pieter; Veloso, Anabela; Yang, Sheng; Serbulova, Kateryna; Ryckaert, Julien (2024) -
ESD protection diodes in sub-5nm gate-all-around nanosheet technologies
Chen, Shih-Hung; Veloso, Anabela; Mertens, Hans; Hellings, Geert; Simicic, Marko; Chen, Wen Chieh; Wu, Wei-Min; Serbulova, Kateryna; Linten, Dimitri; Horiguchi, Naoto (2020) -
Evaluating latchup (LU) risk in advanced CMOS technologies
Serbulova, Kateryna; Groeseneken, Guido; Chen, Shih-Hung; Hellings, Geert (2020) -
Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO
Serbulova, Kateryna; Chen, Shih-Hung; Hellings, Geert; Veloso, Anabela; Jourdain, Anne; De Boeck, Jo; Groeseneken, Guido; Dentoni Litta, Eugenio; Horiguchi, Naoto (2023) -
Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era
Serbulova, Kateryna; Chen, Shih-Hung; Hellings, Geert; Hiblot, Gaspard; Veloso, Anabela; Jourdain, Anne; De Boeck, Jo; Groeseneken, Guido; Horiguchi, Naoto (2021) -
Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era
Serbulova, Kateryna; Chen, Shih-Hung; Hellings, Geert; Veloso, Anabela; Jourdain, Anne; De Boeck, Jo; Groeseneken, Guido (2024) -
Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications
Serbulova, Kateryna; Qiu, Zi-En; Chen, Shih-Hung; Grill, Alexander; Kao, Kuo-Hsing; De Boeck, Jo; Groeseneken, Guido (2024) -
TCAD study of latch-up sensitivity to wafer thinning below 500 nm
Hiblot, Gaspard; Serbulova, Kateryna; Hellings, Geert; Chen, Shih-Hung (2021)