Browsing by author "Lu, Zhichao"
Now showing items 1-4 of 4
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A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C
Lu, Zhichao; Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; De Keersgieter, An; Schwarzenbach, W.; Bonnin, O.; Bourdelle, K.K.; Nguyen, B.-Y.; Mazure, C.; Altimime, Laith; Jurczak, Gosia (2010) -
BJT mode endurance on a 1T-RAM bulk FinFET device
Aoulaiche, Marc; Collaert, Nadine; Degraeve, Robin; Lu, Zhichao; De Wachter, Bart; Jurczak, Gosia; Altimime, Laith (2010) -
Floating body cell memory
Jurczak, Gosia; Collaert, Nadine; Aoulaiche, Marc; Lu, Zhichao; Altimime, Laith (2010) -
Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages
Lu, Zhichao; Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; De Keersgieter, An; Fossum, Jerry; Altimime, Laith; Jurczak, Gosia (2010)