Browsing by author "Chauhan, Y."
Now showing items 1-4 of 4
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A new charge based compact model for lateral asymmetric MOSFET and its application to high voltage MOSFET modeling
Chauhan, Y.; Krummenacher, F.; Anghel, C.; Gillon, R.; Bakeroot, Benoit; Declercq, M.; Ionescu, A. (2007-01) -
Compact modeling of lateral nonuniform doping in high-voltage MOSFETs
Chauhan, Y.; Krummenacher, F.; Gillon, R.; Bakeroot, Benoit; Declercq, M.; Ionescu, A. (2007) -
Consideration of UFET architecture for the 5nm node and beyond logic transistor
Kumar Das, Uttam; Eneman, Geert; Velampati, Ravi; Chauhan, Y.; Jinesh, K.; Bhattacharya, T. (2018) -
Consideration of UFET architecture for the 5nm node and beyond logic transistor
Kumar Das, Utta; Eneman, Geert; Velampati, Ravi; Chauhan, Y.; Jinesh, K.; Bhattacharya, T. (2018)