Consideration of UFET architecture for the 5nm node and beyond logic transistor

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Authors
Kumar Das, Utta; Eneman, Geert; Velampati, Ravi; Chauhan, Y.; Jinesh, K.; Bhattacharya, T.
Conference
Silicon Nanoelectronics Workshop
Title
Consideration of UFET architecture for the 5nm node and beyond logic transistor
Publication type
Proceedings paper
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