Publication:
Consideration of UFET architecture for the 5nm node and beyond logic transistor
Date
| dc.contributor.author | Kumar Das, Utta | |
| dc.contributor.author | Eneman, Geert | |
| dc.contributor.author | Velampati, Ravi | |
| dc.contributor.author | Chauhan, Y. | |
| dc.contributor.author | Jinesh, K. | |
| dc.contributor.author | Bhattacharya, T. | |
| dc.contributor.imecauthor | Eneman, Geert | |
| dc.contributor.orcidimec | Eneman, Geert::0000-0002-5849-3384 | |
| dc.date.accessioned | 2021-10-25T21:18:47Z | |
| dc.date.available | 2021-10-25T21:18:47Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/31091 | |
| dc.source.beginpage | 1 | |
| dc.source.conference | Silicon Nanoelectronics Workshop | |
| dc.source.conferencedate | 17/06/2018 | |
| dc.source.conferencelocation | Honolulu USA | |
| dc.title | Consideration of UFET architecture for the 5nm node and beyond logic transistor | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
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