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Consideration of UFET architecture for the 5nm node and beyond logic transistor
Publication:
Consideration of UFET architecture for the 5nm node and beyond logic transistor
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Date
2018
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Kumar Das, Utta
;
Eneman, Geert
;
Velampati, Ravi
;
Chauhan, Y.
;
Jinesh, K.
;
Bhattacharya, T.
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1846
since deposited on 2021-10-25
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Acq. date: 2026-02-24
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Statistics
Views
1846
since deposited on 2021-10-25
1
last month
Acq. date: 2026-02-24
Citations