Browsing by author "Gupta, Mohit"
Now showing items 1-20 of 21
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A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
Gupta, Mohit; Weckx, Pieter; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Cosemans, Stefan; Ryckaert, Julien; Dehaene, Wim (2021) -
Challenges with SOT-MRAM integration towards N5 node and beyond
Gupta, Mohit; Perumkunnil, Manu; Yasin, Farrukh; Mirabelli, Gioele; Garello, K.; Gupta, Anshul; Furnemont, Arnaud; Kar, Gouri Sankar (2022) -
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out
Singh, Abhairaj; Zahedi, Mahdi; Shahroodi, Taha; Gupta, Mohit; Gebregiorgis, Anteneh; Komalan, Manu; Joshi, Rajiv, V; Catthoor, Francky; Bishnoi, Rajendra; Hamdioui, Said (2022) -
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications
Gupta, Mohit; Perumkunnil, Manu; Fantini, Andrea; Alinezhad Chamazcoti, Saeideh; Kim, Woojin; Garcia Bardon, Marie; Kar, Gouri Sankar; Furnemont, Arnaud (2022) -
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications
Gupta, Mohit; Perumkunnil, Manu; Biswas, Dwaipayan; Alinezhad Chamazcoti, Saeideh; Kar, Gouri Sankar; Furnemont, Arnaud; Ryckaert, Julien (2023-07-21) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
Alinezhad Chamazcoti, Saeideh; Gupta, Mohit; Oh, Hyungrock; Evenblij, Timon; Catthoor, Francky; Perumkunnil, Manu; Kar, Gouri Sankar; Furnemont, Arnaud (2023) -
Feasibility analysis of embedded MRAM solutions at advanced process nodes
Perumkunnil, Manu; Gupta, Mohit; Rao, Siddharth; Kim, Woojin; Yasin, Farrukh; Couet, Sebastien; Furnemont, Arnaud; Kar, Gouri Sankar (2022) -
Field-Free Spin-Orbit Torque Driven Switching of Perpendicular Magnetic Tunnel Junction through Bending Current
Kateel, Vaishnavi; Krizakova, Viola; Rao, Siddharth; Cai, Kaiming; Gupta, Mohit; Gama Monteiro Junior, Maxwel; Yasin, Farrukh; Soree, Bart; De Boeck, Jo; Couet, Sebastien; Gambardella, Pietro; Kar, Gouri Sankar; Garello, Kevin (2023) -
First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories
Cai, Kaiming; Talmelli, Giacomo; Fan, Kaiquan; Van Beek, Simon; Kateel, Vaishnavi; Gupta, Mohit; Gama Monteiro Junior, Maxwel; Ben Chroud, Mohamed; Jayakumar, Ganesh; Trovato, Anna; Rao, Siddharth; Kar, Gouri Sankar; Couet, Sebastien (2022) -
High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node
Gupta, Mohit; Perumkunnil, Manu; Garello, Kevin; Rao, Siddharth; Yasin, Farrukh; Kar, Gouri Sankar; Furnemont, Arnaud (2020) -
Impact of interconnects enhancement on SRAM design beyond 5nm technology node
Gupta, Mohit; Weckx, Pieter; Perumkunnil, Manu; Ryckaert, Julien (2023) -
Magnetic Domain Wall Memory: A DTCO study for Memory Applications
Gupta, Mohit; Rao, Siddharth; Kar, Gouri Sankar; Couet, Sebastien (2023) -
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices
Marinelli, Tommaso; Gomez Perez, Jignacio; Tenllado, Christian; Komalan, Manu; Gupta, Mohit; Catthoor, Francky (2022) -
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
Weckx, Pieter; Ryckaert, Julien; Dentoni Litta, Eugenio; Yakimets, Dmitry; Matagne, Philippe; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Baert, Rogier; Gupta, Mohit; Oniki, Yusuke; Ragnarsson, Lars-Ake; Horiguchi, Naoto; Spessot, Alessio; Verkest, Diederik (2019) -
Optimization of read and write performance of SRAMs for node 5nm and beyond
Shaik, Khaja Ahmad; Gupta, Mohit; Weckx, Pieter; Spessot, Alessio (2019) -
SRAM enablement beyond N7: a BTI study
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Kaczer, Ben; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
SRAM with buried power distribution to improve write margin and performance in advanced technology nodes
Salahuddin, Shairfe Muhammad; Shaik, Khaja Ahmad; Gupta, Anshul; Chava, Bharani; Gupta, Mohit; Weckx, Pieter; Ryckaert, Julien; Spessot, Alessio (2019) -
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes
Garcia-Redondo, F.; Rao, Siddharth; Gupta, Mohit; Perumkunnil, Manu; Xiang, Yang; Abdi, Dawit; Van Beek, Simon; Couet, Sebastien; Garcia Bardon, Marie (2023)