Browsing by author "Gerousis, V."
Now showing items 1-4 of 4
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Impact of a SADP flow on the design and process for N10/N7 layers
Gillijns, Werner; Sherazi, Yasser; Trivkovic, Darko; Chava, Bharani; Vandewalle, B.; Gerousis, V.; Raghavan, Praveen; Ryckaert, Julien; Mercha, Abdelkarim; Verkest, Diederik; McIntyre, Greg; Ronse, Kurt (2015) -
Low track height standard cell design in iN7 using scaling boosters
Sherazi, Yasser; Jha, Chaitanya; Rodopoulos, Dimitrios; Debacker, Peter; Chava, Bharani; Mattii, Luca; Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Gerousis, V.; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Ryckaert, Julien (2017) -
Metal stack optimization for low-power and high-density for N7-N5
Raghavan, Praveen; Firouzi, Farshad; Matti, L.; Debacker, Peter; Baert, Rogier; Sherazi, Yasser; Trivkovic, Darko; Gerousis, V.; Dusa, Mircea; Ryckaert, Julien; Tokei, Zsolt; Verkest, Diederik; McIntyre, Greg; Ronse, Kurt (2016) -
Track height reduction for standard-cell in below 5nm node: How low can you go?
Sherazi, Yasser; Chae, Jung Kyu; Debacker, Peter; Mattii, Luca; Raghavan, Praveen; Gerousis, V.; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Spessot, Alessio; Ryckaert, Julien (2018)