Browsing by author "Rynders, Luc"
Now showing items 1-20 of 27
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21 nm Pitch dual-damascene BEOL process integration with full barrierless Ru metallization
Vega Gonzalez, Victor; Wilson, Chris; Paolillo, Sara; Decoster, Stefan; Mao, Ming; Versluijs, Janko; Blanco, Victor; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Varela Pedreira, Olalla; Lesniewska, Alicja; Heylen, Nancy; El-Mekki, Zaid; van der Veen, Marleen; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Jourdan, Nicolas; Ciofi, Ivan; Contino, Antonino; Boccardi, Guillaume; Lariviere, Stephane; De Wachter, Bart; Vancoille, Eric; Lazzarino, Frederic; Ercken, Monique; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Pardons, Katrien; Barla, Kathy; Tokei, Zsolt (2019) -
28nm-pitch Ru interconnects patterned with 0.33NA-EUV single exposure
Das, Sayantan; Kisson, Nicola; Mahmud Ul Hasan, Hasan MD; Rynders, Luc; Kljucar, Luka; Halder, Sandip; Leray, Philippe; Dusa, Mircea; Rio, David; Mohsen, Mahmoud; Spence, Chris; De Poortere, Etienne (2021) -
A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core
Gyselinckx, Bert; Rynders, Luc; Engels, Marc; Bolsens, Ivo (1997) -
A hardware virtual machine for networked reconfiguration
Ha, Y.; Schaumont, Patrick; Engels, Marc; Vernalde, Serge; Potargent, Freddy; Rynders, Luc; De Man, Hugo (2000) -
A methodology and design environment for DSP ASIC fixed point refinement
Cmar, Radim; Rynders, Luc; Schaumont, Patrick; Vernalde, Serge; Bolsens, Ivo (1999) -
A programming environment for the design of complex high speed ASICs
Schaumont, Patrick; Vernalde, Serge; Rynders, Luc; Engels, Marc; Bolsens, Ivo (1998) -
A scalable architecture to support networked reconfiguration
Ha, Y.; Schaumont, Patrick; Rynders, Luc; Vernalde, Serge; Engels, Marc; De Man, Hugo (1999) -
Building heterogeneous platform simulators in C++ for fun and profit
Pasko, Robert; Rynders, Luc (2005-09) -
Combined simulation and emulation setup for complex image processing algorithms in VHDL
Vanhoof, Bart; Rynders, Luc; Last, Stijn; Botterman, Ivan (2009) -
Design space exploration tool flow for MPSoC embedded design
Avasare, Prabhat; Couvreur, Chantal; Vanmeerbeeck, Geert; De Greef, Eddy; Ashby, Tom; Baert, Rogier; Wuyts, Roel; Stahl, Richard; D'Hondt, Maja; Rynders, Luc; Nollet, Vincent (2010) -
Efficient implementation of pipelined 2D-DCT processor using single 1D-FFT block
Pasko, Robert; Marescaux, Théodore; Rynders, Luc; Vernalde, Serge (2001) -
High level analysis of clock regions in a C++ system description
Rynders, Luc; Schaumont, Patrick; Vernalde, Serge; Bolsens, Ivo (2000) -
High-level simulation and prototyping of software components using SystemC
Pasko, Robert; Rynders, Luc; Vernalde, Serge (2003-09) -
High-performance flexible all-digital quadrature up and down converter chip
Pasko, Robert; Rynders, Luc; Schaumont, Patrick; Vernalde, Serge; Durackova, D. (2000) -
High-performance flexible all-digital quadrature up and down converter chip
Pasko, Robert; Rynders, Luc; Schaumont, Patrick; Vernalde, Serge; Durackova, D. (2001) -
MPEG-4 video decoder
Cupak, Miroslav; Rynders, Luc (2005) -
OCAPI-XL based approach
Cupak, Miroslav; Rynders, Luc (2005) -
Performance analysis for identification of (sub)task-level parallelism in Java
Stahl, Richard; Pasko, Robert; Rynders, Luc; Verkest, Diederik; Vernalde, Serge; Lauwereins, Rudy; Catthoor, Francky (2003-09) -
Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations
Vega Gonzalez, Victor; Montero Alvarez, Daniel; Versluijs, Janko; Varela Pedreira, Olalla; Jourdan, Nicolas; Puliyalil, Harinarayanan; Chehab, Bilal; Peissker, Tobias; Haider, Ali; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Le, Quoc Toan; Bazzazian, Nina; Heylen, Nancy; van der Veen, Marleen; El-Mekki, Zaid; Webers, Tomas; Vats, H.; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Gillijns, Werner; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Ciofi, Ivan; De Wachter, Bart; Swerts, Johan; Grieten, Eva; Ercken, Monique; Kim, Ryan Ryoung han; Croes, Kristof; Leray, Philippe; Jaysankar, Manoj; Nagesh, Nishanth; Ramakers, Leon; Murdoch, Gayle; Park, Seongho; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium
Vega Gonzalez, Victor; Puliyalil, Harinarayanan; Versluijs, Janko; Lesniewska, Alicja; Varela Pedreira, Olalla; Baert, Rogier; Paolillo, Sara; Decoster, Stefan; Schleicher, Filip; Montero Alvarez, Daniel; Bekaert, Joost; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Teugels, Lieve; Heylen, Nancy; Jourdan, Nicolas; El-Mekki, Zaid; van der Veen, Marleen; Ciofi, Ivan; Briggs, Basoene; Heijlen, Jeroen; Dupas, Luc; De Wachter, Bart; Vancoille, Eric; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Demonie, Ingrid; Lazzarino, Frederic; Ercken, Monique; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Jaysankar, Manoj; Wilson, Chris; Murdoch, Gayle; Tokei, Zsolt (2020)