Browsing by author "Debacker, Peter"
Now showing items 1-20 of 84
-
3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020) -
5nm: has the time for a device change come?
Raghavan, Praveen; Garcia Bardon, Marie; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Baert, Rogier; Debacker, Peter; Verkest, Diederik; Thean, Aaron (2016) -
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in -Memory Analog Matrix -Vector-Multiplier for DNN Acceleration
Papistas, Ioannis; Cosemans, Stefan; Rooseleer, Bram; Doevenspeck, Jonas; Na, Myung Hee; Mallik, Arindam; Debacker, Peter; Verkest, Diederik (2021) -
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W
Gupta, Mohit; Cosemans, Stefan; Debacker, Peter; Dehaene, Wim (2023) -
A compact integrated plasmonic modulator
Maes, Bjorn; Moens, Bart; Debacker, Peter; Bienstman, Peter (2009) -
A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs
Evenblij, Timon; Perumkunnil, Manu; Catthoor, Francky; Sakhare, Sushil; Debacker, Peter; Kar, Gouri Sankar; Furnemont, Arnaud; Bueno, Nicolas; Gomez-Perez, Ignacio; Tenllado, Christian (2019) -
A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes
Nibhanupudi, S. S. Teja; Prasad, Divya; Das, Shidhartha; Zografos, Odysseas; Robinson, Alex; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Ryckaert, Julien; Hellings, Geert; Myers, James; Cline, Brian; Kulkarni, Jaydeep P. (2022-07-07) -
A processor based multi-standard low-power LDPC engine for multi-GPS wireless communication
Li, Meng; Naessens, Frederik; Li, Min; Debacker, Peter; Desset, Claude; Raghavan, Praveen; Dejonghe, Antoine; Van der Perre, Liesbet (2013) -
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators
Yang, Simei; Bhattacharjee, Debjyoti; Baapanapalli Yadaiah, Vinay Kumar; Chatterjee, Saikat; De, Sayandip; Debacker, Peter; Verkest, Diederik; Mallik, Arindam; Catthoor, Francky (2022-06-13) -
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard
Li, Meng; Naessens, Frederik; Debacker, Peter; Raghavan, Praveen; Desset, Claude; Li, Min; Dejonghe, Antoine; Van der Perre, Liesbet (2013) -
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS
Li, Meng; Weijers, Jan-Willem; Derudder, Veerle; Vos, Ilse; Rykunov, Maxim; Dupont, Steven; Debacker, Peter; Dewilde, Andy; Huang, Yanxiang; Van der Perre, Liesbet; Van Thillo, Wim (2015) -
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Sherazi, Yasser; Chava, Bharani; Debacker, Peter; Garcia Bardon, Marie; Schuddinck, Pieter; Firouzi, Farshad; Raghavan, Praveen; Mercha, Abdelkarim; Verkest, Diederik; Ryckaert, Julien (2016) -
Biosensors in silicon on insulator
Bienstman, Peter; De Vos, Katrien; Claes, Tom; Debacker, Peter; Baets, Roel; Girones, Jordi; Schacht, Etienne (2009) -
Bulk sensing experiments using a surface-plasmon interferometer
Debacker, Peter; Baets, Roel; Bienstman, Peter (2009-09) -
Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm
Prasad, D.; Nibhanupudi, S.; Das, S.; Zografos, Odysseas; Chehab, Bilal; Sarkar, Satadru; Baert, Rogier; Robinson, A.; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Kulkarni, J.; Cline, B.; Sinha, S. (2019) -
Capturing true workload dependency of BTI-induced degradation in CPU components
Stamoulis, Dimitrios; Corbetta, Simone; Rodopoulos, Dimitrios; Weckx, Pieter; Debacker, Peter; Meyer H., Brett; Kaczer, Ben; Raghavan, Praveen; Soudris, Dimitrios; Catthoor, Francky; Zilic, Zeljko (2016) -
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization
Chen, Rongmei; Chen, Lin; Liang, Jie; Cheng, Yuanqing; Elloumi, Souhir; Lee, Jaehyun; Xu, Kangwei; Georgiev, Vihar P.; Ni, Kai; Debacker, Peter; Asenov, Asen; Todri-Sanial, Aida (2022) -
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part II: CNT Interconnect Optimization
Chen, Rongmei; Chen, Lin; Liang, Jie; Cheng, Yuanqing; Elloumi, Souhir; Lee, Jaehyun; Xu, Kangwei; Georgiev, Vihar P.; Ni, Kai; Debacker, Peter; Asenov, Asen; Todri-Sanial, Aida (2022) -
CFET standard-cell design down to 3Track height for node 3nm and below
Sherazi, Yasser; Chae, Jung Kyu; Debacker, Peter; Mattii, Luca; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Spessot, Alessio; Dounde, Amit; Ryckaert, Julien (2019) -
Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing
Caselli, Michele; Papistas, Ioannis; Cosemans, Stefan; Mallik, Arindam; Debacker, Peter; Verkest, Diederik (2021)