Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

Chen, Rongmei; Chen, Lin; Liang, Jie; Cheng, Yuanqing; Elloumi, Souhir; Lee, Jaehyun; Xu, Kangwei; Georgiev, Vihar P.; Ni, Kai; Debacker, Peter; Asenov, Asen; Todri-Sanial, Aida

doi:10.1109/tvlsi.2022.3146125

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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

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2022

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https://doi.org/10.1109/tvlsi.2022.3146125

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

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Acq. date: 2026-07-16

1424 since deposited on 2023-05-04

Acq. date: 2026-07-16

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

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