Publication:

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

Date

2022
Journal article
https://doi.org/10.1109/TVLSI.2022.3146125
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dc.contributor.authorChen, Rongmei
dc.contributor.authorChen, Lin
dc.contributor.authorLiang, Jie
dc.contributor.authorCheng, Yuanqing
dc.contributor.authorElloumi, Souhir
dc.contributor.authorLee, Jaehyun
dc.contributor.authorXu, Kangwei
dc.contributor.authorGeorgiev, Vihar P.
dc.contributor.authorNi, Kai
dc.contributor.authorDebacker, Peter
dc.contributor.authorAsenov, Asen
dc.contributor.authorTodri-Sanial, Aida
dc.contributor.imecauthorChen, Rongmei
dc.contributor.imecauthorDebacker, Peter
dc.contributor.orcidextLiang, Jie::0000-0002-0595-8598
dc.contributor.orcidextCheng, Yuanqing::0000-0003-2477-314X
dc.contributor.orcidextXu, Kangwei::0000-0003-4221-6830
dc.contributor.orcidextGeorgiev, Vihar P.::0000-0001-6473-2508
dc.contributor.orcidextTodri-Sanial, Aida::0000-0001-8573-2910
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.date.accessioned2023-05-04T13:22:57Z
dc.date.available2023-05-04T13:22:57Z
dc.date.embargo2023-05-04
dc.date.issued2022
dc.description.wosFundingTextThis work was supported in part by the European Commission H2020 CONNECT Project (http://www.connect-h2020.eu/) under Grant 688612 and in part by the Marie Sklodowska-Curie Individual Fellowship under Grant 894805, H-3D-SOC.
dc.identifier.doi10.1109/TVLSI.2022.3146125
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41561
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage432
dc.source.endpage439
dc.source.issue4
dc.source.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
dc.source.numberofpages8
dc.source.volume30
dc.subject.keywordsVIRTUAL-SOURCE MODEL
dc.subject.keywordsCAPACITANCE
dc.subject.keywordsARRAYS
dc.subject.keywordsCELL
dc.subject.keywordsFETS
dc.title

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

dc.typeJournal article
dspace.entity.typePublication
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