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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications
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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications
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Date
2023
Journal article
https://doi.org/10.1016/j.sse.2023.108729
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Silva, V. C. P.
;
Martino, J. A.
;
Simoen, Eddy
;
Veloso, Anabela
;
Agopian, P. G. D.
Journal
SOLID-STATE ELECTRONICS
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840
since deposited on 2023-10-15
Acq. date: 2026-01-07
Citations
Metrics
Views
840
since deposited on 2023-10-15
Acq. date: 2026-01-07
Citations