Publication:

Trades-off between line edge roughness and error-correcting codes requirements for NAND Flash Memories

Date

2012
Journal article
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dc.contributor.authorPoliakov, Pavel
dc.contributor.authorBlomme, Pieter
dc.contributor.authorVaglio Pret, Alessandro
dc.contributor.authorMiranda Corbalan, Miguel
dc.contributor.authorGronheid, Roel
dc.contributor.authorVerkest, Diederik
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorVaglio Pret, Alessandro
dc.contributor.imecauthorGronheid, Roel
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-20T14:42:05Z
dc.date.available2021-10-20T14:42:05Z
dc.date.issued2012
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21318
dc.source.beginpage525
dc.source.endpage529
dc.source.issue3
dc.source.journalMicroelectronics Reliability
dc.source.volume52
dc.title

Trades-off between line edge roughness and error-correcting codes requirements for NAND Flash Memories

dc.typeJournal article
dspace.entity.typePublication
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