Publication:

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

Date

2019
Proceedings Paper
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dc.contributor.authorWeckx, Pieter
dc.contributor.authorRyckaert, Julien
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorMatagne, Philippe
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorJang, Doyoung
dc.contributor.authorChehab, Bilal
dc.contributor.authorBaert, Rogier
dc.contributor.authorGupta, Mohit
dc.contributor.authorOniki, Yusuke
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorSpessot, Alessio
dc.contributor.authorVerkest, Diederik
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorJang, Doyoung
dc.contributor.imecauthorChehab, Bilal
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorOniki, Yusuke
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecOniki, Yusuke::0000-0002-6619-1327
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-27T23:19:00Z
dc.date.available2021-10-27T23:19:00Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34426
dc.source.beginpage871
dc.source.conferenceIEEE Electron Devices Meeting - IEDM
dc.source.conferencedate9/12/2019
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage874
dc.title

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

dc.typeProceedings paper
dspace.entity.typePublication
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