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Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency

 
dc.contributor.authorChuang, Po-Yao
dc.contributor.authorLorenzelli, Francesco
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.imecauthorChuang, Po-Yao
dc.contributor.imecauthorLorenzelli, Francesco
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecChuang, Po-Yao::0000-0001-7325-8836
dc.contributor.orcidimecLorenzelli, Francesco::0000-0001-6465-7157
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2024-06-06T07:51:49Z
dc.date.available2023-12-14T17:35:40Z
dc.date.available2024-06-06T07:51:49Z
dc.date.issued2023
dc.identifier.doi10.1109/ITC-Asia58802.2023.10301169
dc.identifier.eisbn979-8-3503-1281-2
dc.identifier.issn2768-0681
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43250
dc.publisherIEEE
dc.source.conference7th IEEE International Test Conference in Asia (ITC-Asia)
dc.source.conferencedateSEP 12-15, 2023
dc.source.conferencelocationMatsue
dc.source.journalN/A
dc.source.numberofpages6
dc.title

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency

dc.typeProceedings paper
dspace.entity.typePublication
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