Publication:

Direct extraction of contact and S/D epi access resistance components on 45nm Gate Pitch NS-based n-FET devices for the 2nm node

Date

2024
Proceedings Paper
https://doi.org/10.1109/iedm50854.2024.10873517
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dc.contributor.authorEyben, Pierre
dc.contributor.authorPondini, Andrea
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorMertens, Hans
dc.contributor.authorChiarella, Thomas
dc.contributor.authorPorret, Clément
dc.contributor.authorRosseel, Erik
dc.contributor.authorSarkar, Ritam
dc.contributor.authorHosseini, Maryam
dc.contributor.authorZhou, X.
dc.contributor.authorWouters, Lennaert
dc.contributor.authorMatagne, Philippe
dc.contributor.authorMitard, Jerome
dc.contributor.authorHoriguchi, Naoto
dc.date.accessioned2026-05-11T09:31:23Z
dc.date.available2026-05-11T09:31:23Z
dc.date.createdwos2026-03-18
dc.date.issued2024
dc.description.abstractWe report on a new methodology to perform direct extraction of contact and source/drain epi resistance components in NS-based n-FET device (n-NSFET) with 45nm Gate Pitch and 16nm Gate Length. We have combined this method with advanced metrology (XTEM and scalpel SSRM) to analyze the device topology and carrier distribution, and to extract contact resistivity. We have investigated the impact of post S/D epi spike anneal and compared the results with reference contact resistivity values extracted on TLM test-structures. We have used this information to calibrate a TCAD deck and propose solutions to boost device performance.
dc.identifier.doi10.1109/iedm50854.2024.10873517
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59412
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedate2025-12-07
dc.source.conferencelocationSan Francisco
dc.source.journal2024 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

Direct extraction of contact and S/D epi access resistance components on 45nm Gate Pitch NS-based n-FET devices for the 2nm node

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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