Publication:

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

 
dc.contributor.authorGiacomin, Edouard
dc.contributor.authorCatthoor, Francky
dc.contributor.authorGaillardon, Pierre-Emmanuel
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2022-03-30T09:26:01Z
dc.date.available2021-11-11T03:04:05Z
dc.date.available2022-03-23T14:44:34Z
dc.date.available2022-03-30T09:26:01Z
dc.date.issued2021
dc.identifier.doi10.1109/ISCAS51556.2021.9401685
dc.identifier.eisbn978-1-7281-9201-7
dc.identifier.issn0271-4302
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38417
dc.publisherIEEE
dc.source.conferenceIEEE International Symposium on Circuits and Systems (IEEE ISCAS)
dc.source.conferencedateMAY 22-28, 2021
dc.source.conferencelocationDaegu
dc.source.journalna
dc.source.numberofpages5
dc.subject.keywords3D monolithic, Area-Efficient Multiplier
dc.title

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

dc.typeProceedings paper
dspace.entity.typePublication
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