Publication:
System-level assessment and area performance evaluation of spin wave logic circuits
Date
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-9998-8009 | |
| cris.virtual.orcid | 0000-0002-4157-1956 | |
| cris.virtual.orcid | 0000-0002-3861-0168 | |
| cris.virtualsource.department | 9d79c6fb-8d31-4942-9cf4-f2da02aba2a1 | |
| cris.virtualsource.department | f9b525b6-66d0-4e40-8dd4-46fc733e347c | |
| cris.virtualsource.department | b1e77fca-3064-486a-843f-8df6743d3ff2 | |
| cris.virtualsource.orcid | 9d79c6fb-8d31-4942-9cf4-f2da02aba2a1 | |
| cris.virtualsource.orcid | f9b525b6-66d0-4e40-8dd4-46fc733e347c | |
| cris.virtualsource.orcid | b1e77fca-3064-486a-843f-8df6743d3ff2 | |
| dc.contributor.author | Zografos, Odysseas | |
| dc.contributor.author | Raghavan, Praveen | |
| dc.contributor.author | Amaru, Luca | |
| dc.contributor.author | Soree, Bart | |
| dc.contributor.author | Lauwereins, Rudy | |
| dc.contributor.imecauthor | Zografos, Odysseas | |
| dc.contributor.imecauthor | Soree, Bart | |
| dc.contributor.imecauthor | Lauwereins, Rudy | |
| dc.contributor.orcidimec | Zografos, Odysseas::0000-0002-9998-8009 | |
| dc.contributor.orcidimec | Soree, Bart::0000-0002-4157-1956 | |
| dc.contributor.orcidimec | Lauwereins, Rudy::0000-0002-3861-0168 | |
| dc.date.accessioned | 2021-10-22T09:01:59Z | |
| dc.date.available | 2021-10-22T09:01:59Z | |
| dc.date.embargo | 9999-12-31 | |
| dc.date.issued | 2014 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/24897 | |
| dc.identifier.url | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6880475 | |
| dc.source.beginpage | 25 | |
| dc.source.conference | IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH | |
| dc.source.conferencedate | 8/07/2014 | |
| dc.source.conferencelocation | Paris France | |
| dc.source.endpage | 30 | |
| dc.title | System-level assessment and area performance evaluation of spin wave logic circuits | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | Original bundle
| |
| Publication available in collections: |