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A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

Date

2012
Journal article
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-6792-7965
cris.virtualsource.department7386c741-e8e9-427f-bca4-f091a80818f8
cris.virtualsource.orcid7386c741-e8e9-427f-bca4-f091a80818f8
dc.contributor.authorRooseleer, Bram
dc.contributor.authorCosemans, Stefan
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorRooseleer, Bram
dc.contributor.imecauthorCosemans, Stefan
dc.contributor.imecauthorDehaene, Wim
dc.date.accessioned2021-10-20T15:29:43Z
dc.date.available2021-10-20T15:29:43Z
dc.date.embargo9999-12-31
dc.date.issued2012
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21426
dc.source.beginpage1784
dc.source.endpage1796
dc.source.issue7
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.volume47
dc.title

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

dc.typeJournal article
dspace.entity.typePublication
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