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Modeling and Analysis of Terminal Capacitances in High-Power Devices: Application to p-GaN Gate HEMTs

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dc.contributor.authorAlaei, Mojtaba
dc.contributor.authorDe Pauw, Herbert
dc.contributor.authorFabris, Elena
dc.contributor.authorDecoutere, Stefaan
dc.contributor.authorDoutreloigne, Jan
dc.contributor.authorLauwaert, Johan
dc.contributor.authorBakeroot, Benoit
dc.contributor.imecauthorAlaei, Mojtaba
dc.contributor.imecauthorDePauw, Herbert
dc.contributor.imecauthorFabris, Elena
dc.contributor.imecauthorDecoutere, Stefaan
dc.contributor.imecauthorDoutreloigne, Jan
dc.contributor.imecauthorBakeroot, Benoit
dc.contributor.orcidimecAlaei, Mojtaba::0000-0002-5815-3654
dc.contributor.orcidimecFabris, Elena::0000-0003-1345-5111
dc.contributor.orcidimecDecoutere, Stefaan::0000-0001-6632-6239
dc.contributor.orcidimecDoutreloigne, Jan::0000-0002-0626-5996
dc.contributor.orcidimecBakeroot, Benoit::0000-0003-4392-1777
dc.date.accessioned2025-08-12T03:59:41Z
dc.date.available2025-08-12T03:59:41Z
dc.date.issued2025-AUG 1
dc.description.wosFundingTextThis work was supported by the ASCENT+ Project funded from the European Union's Horizon 2020 Research and Innovation Program under Grant 871130. The review of this article was arranged by Editor K. Kalna.
dc.identifier.doi10.1109/TED.2025.3593216
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/46052
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage4817
dc.source.endpage4823
dc.source.issue9
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages7
dc.source.volume72
dc.title

Modeling and Analysis of Terminal Capacitances in High-Power Devices: Application to p-GaN Gate HEMTs

dc.typeJournal article
dspace.entity.typePublication
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