Publication:
Gate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical model
Date
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-5218-4046 | |
| cris.virtual.orcid | 0000-0002-8245-9442 | |
| cris.virtual.orcid | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-5849-3384 | |
| cris.virtualsource.department | 715a9ada-0798-46d2-a8ca-4775db9a8e46 | |
| cris.virtualsource.department | f421472b-3c78-4486-a88e-266fc55314cb | |
| cris.virtualsource.department | 2e4899f6-dd27-4b8d-adf7-533ca9064170 | |
| cris.virtualsource.department | db73cf2d-2000-429c-bc92-553a1ef3e876 | |
| cris.virtualsource.orcid | 715a9ada-0798-46d2-a8ca-4775db9a8e46 | |
| cris.virtualsource.orcid | f421472b-3c78-4486-a88e-266fc55314cb | |
| cris.virtualsource.orcid | 2e4899f6-dd27-4b8d-adf7-533ca9064170 | |
| cris.virtualsource.orcid | db73cf2d-2000-429c-bc92-553a1ef3e876 | |
| dc.contributor.author | Eneman, Geert | |
| dc.contributor.author | Simoen, Eddy | |
| dc.contributor.author | Verheyen, Peter | |
| dc.contributor.author | De Meyer, Kristin | |
| dc.contributor.imecauthor | Eneman, Geert | |
| dc.contributor.imecauthor | Simoen, Eddy | |
| dc.contributor.imecauthor | Verheyen, Peter | |
| dc.contributor.imecauthor | De Meyer, Kristin | |
| dc.contributor.orcidimec | Eneman, Geert::0000-0002-5849-3384 | |
| dc.contributor.orcidimec | Simoen, Eddy::0000-0002-5218-4046 | |
| dc.date.accessioned | 2021-10-17T07:00:12Z | |
| dc.date.available | 2021-10-17T07:00:12Z | |
| dc.date.embargo | 9999-12-31 | |
| dc.date.issued | 2008 | |
| dc.identifier.issn | 0018-9383 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/13693 | |
| dc.source.beginpage | 2703 | |
| dc.source.endpage | 2711 | |
| dc.source.issue | 10 | |
| dc.source.journal | IEEE Transactions on Electron Devices | |
| dc.source.volume | 55 | |
| dc.title | Gate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical model | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | Original bundle
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| Publication available in collections: |