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Using neural architecture search to optimize neural networks for embedded devices

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dc.contributor.authorCassimon, Thomas
dc.contributor.authorVanneste, Simon
dc.contributor.authorBosmans, Stig
dc.contributor.authorMercelis, Siegfried
dc.contributor.authorHellinckx, Peter
dc.contributor.imecauthorCassimon, Thomas
dc.contributor.imecauthorVanneste, Simon
dc.contributor.imecauthorBosmans, Stig
dc.contributor.imecauthorMercelis, Siegfried
dc.contributor.imecauthorHellinckx, Peter
dc.contributor.orcidimecCassimon, Thomas::0000-0002-7471-2508
dc.contributor.orcidimecVanneste, Simon::0000-0002-9664-9925
dc.contributor.orcidimecMercelis, Siegfried::0000-0001-9355-6566
dc.date.accessioned2021-10-27T07:51:03Z
dc.date.available2021-10-27T07:51:03Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32649
dc.identifier.urlhttps://doi.org/10.1007/978-3-030-33509-0_64
dc.source.beginpage684
dc.source.conference3PGCIC 2019: Advances on P2P, Parallel, Grid, Cloud and Internet Computing
dc.source.conferencedate7/11/2019
dc.source.conferencelocationAntwerpen Belgium
dc.source.endpage693
dc.title

Using neural architecture search to optimize neural networks for embedded devices

dc.typeProceedings paper
dspace.entity.typePublication
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