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Nemesis: Studying microarchitectural timing leaks in rudimentary CPU interrupt logic

Date

2018
Proceedings Paper
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dc.contributor.authorVan Bulck, Jo
dc.contributor.authorPiessens, Frank
dc.contributor.authorStrackx, Raoul
dc.date.accessioned2021-10-26T06:25:29Z
dc.date.available2021-10-26T06:25:29Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32013
dc.identifier.urlhttps://doi.org/10.1145/3243734.3243822
dc.source.beginpage178
dc.source.conferenceCCS '18 Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security
dc.source.conferencedate15/10/2018
dc.source.conferencelocationtoronto Canada
dc.source.endpage195
dc.title

Nemesis: Studying microarchitectural timing leaks in rudimentary CPU interrupt logic

dc.typeProceedings paper
dspace.entity.typePublication
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