Publication:

Analysis of fractional spur reduction using SD noise cancellation in digital PLL

Date

2009
Proceedings Paper
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-3980-0203
cris.virtualsource.department32d8e58a-5716-42c1-8c08-46738850ae45
cris.virtualsource.orcid32d8e58a-5716-42c1-8c08-46738850ae45
dc.contributor.authorVengattaramane, Kameswaran
dc.contributor.authorCraninckx, Jan
dc.contributor.authorSteyaert, Michiel
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-18T04:39:25Z
dc.date.available2021-10-18T04:39:25Z
dc.date.embargo9999-12-31
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16456
dc.source.beginpage2397
dc.source.conferenceIEEE International Conference on Circuits and Systems - ISCAS
dc.source.conferencedate24/05/2009
dc.source.conferencelocationTaipei Taiwan
dc.source.endpage2400
dc.title

Analysis of fractional spur reduction using SD noise cancellation in digital PLL

dc.typeProceedings paper
dspace.entity.typePublication
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