Electromigration Reliability Analysis of SRAM-based Register Files in GPUs and AI Accelerators

Abstract

The demand for Artificial Intelligence (AI) and large AI models mandates high compute power, driving substantial increases in computational cost, both in terms of energy and hardware resources. From the hardware perspective, training these models typically relies on dataflow architectures such as Graphical Processing Unit (GPU) and dedicated AI accelerators. While performance and energy efficiency are essential, the reliability of these systems is equally critical. Given the time and energy requirements for training, in-field failures are extremely costly. At the same time, higher integration density and smaller feature sizes cause high chip activity and temperature. Combined with prolonged execution times, it increases the failure probabilities. This paper focuses on Electromigration (EM) issues in Static RAM (SRAM)-based register files, which act as the primary link between memory and processing cores in dataflow architectures. Our main contribution is a comprehensive EM analysis, revealing a significantly different EM profile compared to traditional SRAM-based caches. These findings highlight the cruciality of EM concern in the SRAM-based register files and open doors to new mitigation and prevention solutions.