Publication:

Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and below

Date

2005
Presentation
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dc.contributor.authorEyckens, Brenda
dc.contributor.authorCollaert, Nadine
dc.contributor.authorSchaekers, Marc
dc.contributor.authorSleeckx, Erik
dc.contributor.authorEneman, Geert
dc.contributor.authorVerheyen, Peter
dc.contributor.authorRooyackers, Rita
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorSchaekers, Marc
dc.contributor.imecauthorSleeckx, Erik
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecSchaekers, Marc::0000-0002-1496-7816
dc.contributor.orcidimecSleeckx, Erik::0000-0003-2560-6132
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.date.accessioned2021-10-16T01:33:30Z
dc.date.available2021-10-16T01:33:30Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10447
dc.source.conference8th Technical and Scientific Meeting of CREMSI 8th Technical and Scientific Meeting of CREMSI
dc.source.conferencedate20/10/2005
dc.source.conferencelocationFuveau France
dc.title

Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and below

dc.typeOral presentation
dspace.entity.typePublication
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