Publication:
On-chip circuit for massively parallel BTI characterization
Date
| dc.contributor.author | da Silva, Mauricio Banasheski | |
| dc.contributor.author | Kaczer, Ben | |
| dc.contributor.author | Van der Plas, Geert | |
| dc.contributor.author | Wirth, Gilson I. | |
| dc.contributor.author | Groeseneken, Guido | |
| dc.contributor.imecauthor | Kaczer, Ben | |
| dc.contributor.imecauthor | Van der Plas, Geert | |
| dc.contributor.imecauthor | Groeseneken, Guido | |
| dc.contributor.orcidimec | Kaczer, Ben::0000-0002-1484-4007 | |
| dc.contributor.orcidimec | Van der Plas, Geert::0000-0002-4975-6672 | |
| dc.date.accessioned | 2021-10-19T13:00:43Z | |
| dc.date.available | 2021-10-19T13:00:43Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/18762 | |
| dc.source.conference | IEEE International Integrated Reliability Workshop - IIRW | |
| dc.source.conferencedate | 16/10/2011 | |
| dc.source.conferencelocation | Lake Tahoe, CA USA | |
| dc.title | On-chip circuit for massively parallel BTI characterization | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | ||
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