APD Receiver Co-Optimization for Chip-to-Chip Communication on 3D/2.5D Photonic Interposers

Abstract

This work presents the analysis and optimization of a Ge/Si avalanche photodiode (APD) receiver implemented in a 22 nm silicon-on-insulator (SOI) technology node for 3D CMOS photonic links. The fabricated APD achieves a gain–bandwidth product of 250 GHz under a reverse bias of 9 V. Post-layout simulations results show that the receiver improves the optical modulation sensitivity by up to 3 dB compared to a PIN receiver with post-amplification. The APD must be operated in the reverse bias range of [3,9]V to keep the intersymbol interference (ISI) power penalty at 0 dB. These results are obtained through a co-optimization analysis that evaluates the trade-offs between bandwidth, noise, gain, and power consumption of the APD receiver blocks, including the analog front end and sampling stages.