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A 500kHz-10MHz multimode power-performance scalable 83-to-67dB DR CTDS in 90 nm digital CMOS with fexible analog core circuitry

Date

2009
Proceedings Paper
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dc.contributor.authorCrombez, Pieter
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorSteyaert, Michiel
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-17T21:42:03Z
dc.date.available2021-10-17T21:42:03Z
dc.date.embargo9999-12-31
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15142
dc.source.beginpage70
dc.source.conferenceSymposium on VLSI Circuits
dc.source.conferencedate16/06/2009
dc.source.conferencelocationKyoto Japan
dc.source.endpage71
dc.title

A 500kHz-10MHz multimode power-performance scalable 83-to-67dB DR CTDS in 90 nm digital CMOS with fexible analog core circuitry

dc.typeProceedings paper
dspace.entity.typePublication
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