Publication:

Gate-level characterization and reduction of substrate noise in integrated digital circuits

Date

2003
Proceedings Paper
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dc.contributor.authorBadaroglu, Mustafa
dc.contributor.authorWambacq, Piet
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorDonnay, Stephane
dc.contributor.authorGielen, Georges
dc.contributor.authorDe Man, Hugo
dc.contributor.imecauthorBadaroglu, Mustafa
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorDonnay, Stephane
dc.contributor.imecauthorGielen, Georges
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecDonnay, Stephane::0000-0003-2489-4793
dc.date.accessioned2021-10-15T03:59:32Z
dc.date.available2021-10-15T03:59:32Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7165
dc.source.conference1st Flanders Engineering PhD Symposium
dc.source.conferencedate11/12/2003
dc.source.conferencelocationBrussels Belgium
dc.title

Gate-level characterization and reduction of substrate noise in integrated digital circuits

dc.typeProceedings paper
dspace.entity.typePublication
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