Design of reversible logic circuits  by means of control gates

dc.contributor.author	De Vos, Alexis
dc.contributor.author	Desoete, B.
dc.contributor.author	Adamski, A.
dc.contributor.author	Piertzak, P.
dc.contributor.author	Sibinski, M.
dc.contributor.author	Widerski, T.
dc.date.accessioned	2021-10-14T12:50:05Z
dc.date.available	2021-10-14T12:50:05Z
dc.date.embargo	9999-12-31
dc.date.issued	2000
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/4281
dc.source.beginpage	255
dc.source.conference	Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 10th Int. Workshop - PATMOS
dc.source.conferencedate	16/09/2000
dc.source.conferencelocation	Göttingen Germany
dc.source.endpage	264
dc.title	Design of reversible logic circuits by means of control gates
dc.type	Proceedings paper
dspace.entity.type	Publication
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