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Avoiding at-resolution stitching for logic and DRAM applications in high-NA EUV lithography

 
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dc.contributor.authorMiyaguchi, Kenichi
dc.contributor.authorKim, Ryan Ryoung Han
dc.contributor.authorDrissi, Youssef
dc.contributor.authorChang, Chieh-Miao
dc.contributor.authorLee, Jeonghoon
dc.contributor.authorSherazi, Yasser
dc.contributor.authorTrivkovic, Darko
dc.date.accessioned2026-09-17T14:04:00Z
dc.date.available2026-09-17T14:04:00Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractWe present innovative design strategies to eliminate the need for at-resolution field stitching in high-numerical aperture extreme ultraviolet lithography. For logic applications, two complementary approaches at the inter- and intra-cell levels are proposed. These include the insertion of dummy filler cells or relaxed-pitch cells, combined with metal routing blockages, which can be seamlessly implemented within a modified place-and-route flow, thereby simplifying process complexities associated with at-resolution stitching. For dynamic random access memory applications, a die aspect ratio optimization methodology is introduced to maximize mask area utilization and improve manufacturing throughput. Depending on the die arrangement in the full imaging field, two stitching scenarios are identified: an even number of dies in the Y-direction, enabling pitch-tolerant field stitching along the scribe lane, and an odd number of dies, which eliminates the need for critical-dimension-critical stitching at the stitching boundary.
dc.description.wosFundingTextThe at-resolution stitching avoidance technique this paper proposed was previously published as an SPIE conference paper-Proceedings Volume 13425, DTCO and Computational Patterning IV; 134250E (2025) http://dx.doi.org/10.1117/12.3051547. Event: SPIE Advanced Lithography + Patterning, 2025, San Jose, California, United States. We gratefully acknowledge the acceptance of the SPIE Advanced Lithography + Patterning conference and Ryoung-han Kim, Lynn Wang, and Natalia Davydova for inviting us to submit an extended version of the conference paper to the DTCO section in JM3. Darko Trivkovic is a guest editor of the special section in which this paper appears. To maintain transparency and uphold the highest standards of editorial integrity, the peer-review process was managed independently by an editor who oversaw the review and editorial decision-making process. This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (Grant No. 101183266) and Horizon Europe programs (Grant No. 101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland, and Romania. For more information, visit Ref. 8.
dc.identifier.doi10.1117/1.jmm.25.2.021003
dc.identifier.eissn2708-8340
dc.identifier.issn1932-5150
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60416
dc.language.isoeng
dc.provenance.editstepusermeghan.oneill@imec.be
dc.publisherSPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERS
dc.relation.ispartofseriesJournal of Micro/Nanopatterning, Materials, and Metrology
dc.source.beginpage021003
dc.source.issue2
dc.source.journalJOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3
dc.source.numberofpages14
dc.source.volume25
dc.title

Avoiding at-resolution stitching for logic and DRAM applications in high-NA EUV lithography

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-07
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