Challenges and Mitigations of Microbumps Pitch Scaling for Chiplet Applications

Abstract

This article explores the challenges of microbump pitch scaling down to 5 μ m for chiplet applications, including thermocompression bonding (TCB) tool alignment accuracy, fabrication process limitations, coefficient of thermal expansion (CTE) mismatch, metal oxide reduction, and reliability concerns for die-to-wafer (D2W) bonding. An approach called embedded bumps, together with fluxless TCB, is introduced to mitigate the challenges. In addition, it discusses qubit, interposer, and CMOS chips integration in 2.5-D chiplet and 3-D architectures for cold and quantum computing (QC) applications, where indium is used as the solder metal, where successful bonding results for 20- μ m pitch indium bumps are shown.