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A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation

Date

2015
Journal article
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dc.contributor.authorVerbruggen, Bob
dc.contributor.authorTsouhlarakis, Jorgo
dc.contributor.authorYamamoto, Takaya
dc.contributor.authorIriguchi, Masao
dc.contributor.authorMartens, Ewout
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorTsouhlarakis, Jorgo
dc.contributor.imecauthorMartens, Ewout
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-23T00:33:12Z
dc.date.available2021-10-23T00:33:12Z
dc.date.embargo9999-12-31
dc.date.issued2015
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26121
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7102792
dc.source.beginpage2002
dc.source.endpage2011
dc.source.issue9
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.volume50
dc.title

A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation

dc.typeJournal article
dspace.entity.typePublication
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