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Automation of DfT insertion and interconnect test generation for 3D stacked ICs

Date

2011-05
Proceedings Paper
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dc.contributor.authorDeutsch, Sergej
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorKonijnenburg, Mario
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.imecauthorKonijnenburg, Mario
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecKonijnenburg, Mario::0000-0001-8016-0888
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2021-10-19T13:14:40Z
dc.date.available2021-10-19T13:14:40Z
dc.date.issued2011-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18834
dc.identifier.urlhttp://www.eng.auburn.edu/~strouce/NATW2011.html
dc.source.conferenceIEEE North-Atlantic Test Workshop - NATW
dc.source.conferencedate11/05/2011
dc.source.conferencelocationLowell, MA USA
dc.title

Automation of DfT insertion and interconnect test generation for 3D stacked ICs

dc.typeProceedings paper
dspace.entity.typePublication
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