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A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS

Date

2012
Journal article
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dc.contributor.authorNuzzo, Pierluigi
dc.contributor.authorNani, Claudio
dc.contributor.authorArmiento, Costantino
dc.contributor.authorSangiovanni-Vincentelli, Alberto
dc.contributor.authorCraninckx, Jan
dc.contributor.authorVan der Plas, Geert
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.date.accessioned2021-10-20T13:58:22Z
dc.date.available2021-10-20T13:58:22Z
dc.date.embargo9999-12-31
dc.date.issued2012
dc.identifier.issn1549-8328
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21213
dc.source.beginpage80
dc.source.endpage92
dc.source.issue1
dc.source.journalIEEE Transactions on Circuits and Systems I Regular Papers
dc.source.volume59
dc.title

A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS

dc.typeJournal article
dspace.entity.typePublication
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